Download e-book for iPad: Analog IC Reliability in Nanometer CMOS by Elie Maricau

By Elie Maricau

ISBN-10: 1461461626

ISBN-13: 9781461461623

ISBN-10: 1461461634

ISBN-13: 9781461461630

This ebook makes a speciality of modeling, simulation and research of analog circuit getting older. First, all very important nanometer CMOS actual results leading to circuit unreliability are reviewed. Then, transistor getting older compact types for circuit simulation are mentioned and a number of other tools for effective circuit reliability simulation are defined and in comparison. eventually, the influence of transistor getting older on analog circuits is studied. Aging-resilient and aging-immune circuits are pointed out and the effect of expertise scaling is mentioned.

The versions and simulation suggestions defined within the e-book are meant as an relief for equipment engineers, circuit designers and the EDA neighborhood to appreciate and to mitigate the influence of getting older results on nanometer CMOS ICs.

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Extra info for Analog IC Reliability in Nanometer CMOS

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The most harmful mode, the Hard-BD (HBD), provokes the complete loss of the oxide dielectric properties with gate currents in the mA range at standard operation voltages. e. 9 nm) (Degraeve et al. 2008; Pae et al. 2010). e. sub-180 nm CMOS), HBD can be preceded by Soft-BD (SBD). SBD can be observed as a partial loss of the dielectric properties, resulting in a small increase of the gate current and a significant increase of the gate current noise (Gielen et al. 2008). 5 nm thickness), SBD is followed by Progressive-BD (PBD), until final HBD.

2008; Saha 2010). Asenov et al. (2003) have shown that VTH fluctuations induced by local oxide thickness variations become comparable to voltage fluctuations introduced by RDF for sub-30 nm CMOS technologies. Moreover, the variability due to oxide thickness fluctuations is statistically independent from the VTH variations introduced by RDF. HKMG devices allow larger physical oxide thicknesses, but still suffer from large oxide thickness variations due to the roughness of the interface between the silicon and the high-k layer and between the high-k layer and the metal gate (saha 2010).

Although right after SBD a very limited effect is observed (Kaczer et al. 2004), a significant influence on the transistor characteristics is produced at longer times (Kaczer et al. 2004; Cester et al. 2004). This can be modeled as a local mobility reduction in the BD region (Cester et al. 2004). Another important aspect of gate oxide breakdown is the fact that one BD does not necessarily imply circuit failure (Kaczer et al. 2002). Fig. 75 V and T = 140 ◦ C, top curve) and the stress-induced leakage (SILC) at 1V (bottom curve).

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Analog IC Reliability in Nanometer CMOS by Elie Maricau


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